This invention relates to the deposition of a copper onto the surface of a semiconductor substrate comprising vias and trenches and, in particular, to the electroless and electrolytic plating of copper onto a copper seed layer in the vias and trenches using the same copper bath.
An integrated circuit (IC) contains a collection of electrical devices, such as transistors, capacitors, resistors, and diodes, within a dielectric material on a semiconductor. Conductive interconnects connecting discrete devices are referred to as trenches. Additionally, two or more conductive layers, each separated by a dielectric, are typically employed within a given IC to increase its overall performance. Conductive interconnects known as vias are used to connect these distinct conductive layers together. Currently, ICs typically have silicon oxide as the dielectric material and copper as the conductive material.
The demand for manufacturing semiconductor IC devices such as computer chips with high circuit speed, high packing density and low power dissipation requires the downward scaling of feature sizes in ultra-large-scale integration (ULSI) and very-large-scale integration (VLSI) structures. The trend to smaller chip sizes and increased circuit density requires the miniaturization of interconnect features, which severely penalizes the overall performance of the structure because of increasing interconnect resistance and reliability concerns such as electromigration.
Traditionally, such structures had used aluminum and aluminum alloys as the metallization on silicon wafers with silicon dioxide being the dielectric material. In general, openings are formed in the dielectric layer in the shape of vias and trenches after metallization to form the interconnects. Increased miniaturization is reducing the openings to submicron sizes (e.g., 0.5 micron and lower).
To achieve further miniaturization of the device, copper has been introduced to replace aluminum as the metal to form the connection lines and interconnects in the chip. Copper metallization is carried out after forming the interconnects. Copper has a lower resistivity than aluminum and the thickness of a copper line for the same resistance can be thinner than that of an aluminum line. Copper-based interconnects, therefore, represent the future trend in the fabrication of such devices.
The use of copper has introduced a number of requirements into the IC manufacturing process. First, copper has a tendency to diffuse into the semiconductor's junctions, thereby disturbing their electrical characteristics. To combat this occurrence, a barrier layer, such as titanium nitride, tantalum or tantalum nitride, is applied to the dielectric prior to the copper layer's deposition. It is also necessary that the copper be deposited on the barrier layer cost-effectively while ensuring the requisite coverage thickness for carrying signals between the IC's devices. As the architecture of ICs continues to shrink, this requirement proves to be increasingly difficult to satisfy.
One conventional semiconductor manufacturing process is the copper damascene system. Specifically, this system begins by etching the circuit architecture into the substrate's dielectric material. The architecture is comprised of a combination of the aforementioned trenches and vias. Next, a barrier layer is laid over the dielectric to prevent diffusion of the subsequently applied copper layer into the substrate's junctions. Copper is then deposited onto the barrier layer using one of a number of processes, including, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or electrochemical deposition. After the copper layer has been deposited, excess copper is removed from the facial plane of the dielectric, leaving copper in only the etched interconnect features of the dielectric. Subsequent layers are produced similarly before assembly into the final semiconductor package.
Electrochemical deposition, the currently preferred method for applying copper, requires deposition of a thin copper seed layer prior to electrochemical deposition so that the copper has an electrically conductive surface on which to deposit. The copper seed layer is typically applied by PVD or CVD, both of which often have coverage problems, especially in interconnects in the device, such that the copper seed layer is non-continuous and has voids and gaps. These voids and gaps in the copper seed layer impair the ability to subsequently deposit a continuous copper layer by electrochemical deposition. The copper seed layer is typically exposed to an activator liquid to fill in the voids and gaps in the seed layer. For example, the seed layer may be exposed to palladium-tin colloidal suspension to deposit palladium-tin particles on the seed layer and fill the voids and gaps in the seed layer. The deposited palladium carries current across the voids and gaps, thereby facilitating subsequent electrochemical deposition of a continuous copper layer.
Subsequent to activation of the seed layer, a copper seed enhancement layer is typically deposited using an electroless copper plating solution. After deposition of the seed enhancement layer, the filling of the vias and trenches is completed by depositing copper electrolytically using an electrolytic copper plating solution. After depositing the copper seed enhancement layer, typically about 99 percent of their depth remains unfilled. Thus, the majority of the filling process occurs during the electrolytic plating operation.
Although widely used, electrochemical copper deposition processes have drawbacks. For example, each step requires a different plating solution followed by a water rinse before being immersed in the next plating solution. This typically results in increased raw material costs, increased waste disposal costs, increased manufacturing duration, increased capital investment and increased manufacturing costs all of which increase the cost of each integrated circuit. Thus, a need continues to exist for a less expensive, and more consolidated electrochemical copper deposition process.